Transmitters and receivers in typical high-speed digital communication systems convey information as series of symbols. Common binary systems express a logic one symbol value by drawing a first current from a supply-voltage node through a load to produce a voltage representative of a logic one, and a logic zero symbol value by drawing a second current through the load to produce a voltage representative of a logic zero. A receiver then samples the symbols against a reference voltage to recover the original information. When data symbols are conveyed in parallel as sets of symbols, the total current used to represent successive sets of symbols can change dramatically from one signal to the next. The supply current can thus be data dependent.
Power supplies are imperfect. For example, the lines and pads used to convey supply current exhibit parasitic resistive, inductive, and capacitive impedances. Unfortunately, these impedances and the data-dependent supply current together cause the supply voltage to fluctuate, which can introduce errors and reduce speed performance. This problem is referred to by those of skill in the art as simultaneous switching noise, or SSN. Efforts to minimize SSN have focused on improved voltage regulation and reduced supply impedance so the supply better tolerates changes in load current, and the use of balanced symbols patterns or compensation currents to minimize such changes. These efforts have met with considerable success, but there is ever a demand for improved performance.